Why are multipliers 18x18 Bit in FPGAs?
I'm looking at different FPGAs for my dissertation project and I keep seeing that the multiplier blocks are 18x18 bit, why is this? Why are they not 16-bit?
I'm looking at different FPGAs for my dissertation project and I keep seeing that the multiplier blocks are 18x18 bit, why is this? Why are they not 16-bit?
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